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In the Transcript-window we can read the encouraging message Note: Lock tries to open for the right sequence!. The time 3 μs sufficient to try all possible key-press combinations. We can immediately start the simulation with the command run 3us in the Transcript-window. It creates the clock pulses with a period of 20 ns, as we used before. In the file tb_codelock.vhd you find clk <= not clk after 10 ns. NOTE ! Important to get the arrows! vsim -msgmode both -displaymsgmode both tb_codelock Therefore, we write in the Transcript window: We want to test the bench messages to appear (as arrows) at the top of the Wave-window. By the content of the file we can see that it controles the other file codelock.vhd, so that's why it gets the highest order. Now the file is compiled tb_lockmall.vhd. The file tb_lockmall.vhd is not compiled yet, which can be seen on the blue question mark.Ĭhoose the menu Compile and the alternative Compile All. Copy and paste the content of the file tb_lockmall.vhd and then save the file using the same name, tb_lockmall.vhd, among the other files in the project.Īlternatively, you can copy the file tb_lockmall.vhd to the folder with the other files of the project. Testbench In addition to the VHDL code for the lock, we now need another VHDL file for the test bench code.Ĭreate a new empty VHDL-file. This time we choose "Open Project" for continue with our previous MAXsim-project. ModelSim-Altera 10.1d(Quartus II 13.0sp1)Ĭlick on Jumpstart. ModelSim-Altera Starter Edition 13.0.1.232\
#MODELSIM EDITOR SOFTWARE#
Testbench.pdf Select the correct software version - in school there are several versions installed in the Start menu! Altera 13.0.1.232 Web edition\ Testbench in ModelSim Automate the testing of the code lock